Implementation of An Efficient Gate Level Modified Square-Root Carry Select Adder Using HDL

Contribution of this work is reduce the area and power of the CSLA by a simple gate level modification. Based on this modification CSLA  architecture have been developed and compared with the regular SQRT CSLA architecture. Carry Select Adder is one of the best adders used in many data processing processors to perform fast and robust arithmetic functions. It reduces the area and power consumption and became a reputed one. As co pared to the SQRT CSLA it is increased in delay. In this work we have evaluated the performance based delay, area and power with logical effort and through FPGA design by using Xilinx tool for synthesis and simulation for graphical verification by using  Modelsim tool. The result analysis shows that the proposed CSLA structure is better than the regular SQRT CSLA

A Static Time Analysis of 1-bit to 32-page SCA architecture for Logic Test

This research proposes the Static Time Analysis  of  32  page  Single  cycle  access  (SCA)  architecture  for Logic test. The timing analysis of each and very path of Logic test are observed that is setup and hold timings are calculated.  It also eliminates the peak power consumption problem of conventional shift-based scan chains and reduces the activity during shift and capture cycles using Clock-Gating technique. This leads to more realistic circuit behavior during at-speed tests. It enables the complete test to run at much higher frequencies equal or close to the one in functional mode. It will be shown, that a lesser number of test cycles can be achieved compared to other published solutions. The test cycle per net based on a simple test pattern generator algorithm without test pattern compression is below 1 for larger designs and is independent of the design size. The structure allows an additional on-chip debugging signal visibility for each register. The method is backward compatible to full scan designs and existing test pattern generators and simulators can be used with a minor enhancement. It is shown how to combine the proposed solution with built-in self-test  (BIST)  and  massive parallel   scan   chains.   The   results   are   observed   on   Xilinx XC3s1600e-5fgg48